Shadow Register File Architecture: A Mechanism to Reduce Context Switch Latency

In a multiprocessing environment context switch plays an important role in the overall performance of the system. The context switch latency affects the execution time of a process. In this paper we propose certain architectural modifications to reduce context switch latency. A dedicated hardware unit performs context switching operations with the help of Shadow Register File, simultaneously during the normal execution of the processor. The working of the architecture along with state transition diagram is explained in the paper.